fpgatools package¶

fpgatools.FPGA_Tools module¶

class fpgatools.FPGA_Tools.TreeComboBox(*args)¶

Bases: PyQt5.QtWidgets.QComboBox

Nested combobox, which will generate I/O groups.

Parameters: QComboBox (class) – Inherit from QComboBox

eventFilter(obj, event)¶

Sets points parent’s event to child’s event.

Parameters

obj – parent object
event – parent event

Returns

hidePopup()¶

Hides root’s combobox popup.

Returns

selectIndex(index)¶

Sets parent index to point to the new tree combobox.

Parameters: index (class) – Parent object
Returns

showPopup()¶

Sets root model index to point to the nested combobox.

Returns

class fpgatools.FPGA_Tools.UiMainWindow¶

Bases: object

Main window class.

add_custom_pinout()¶

Adds custom FPGA pinout to the list.

Returns

all_port = [{'Name': 'Nexys 4', 'Switch': {'SW0': 'U9', 'SW1': 'U8', 'SW2': 'R7', 'SW3': 'R6', 'SW4': 'R5', 'SW5': 'V7', 'SW6': 'V6', 'SW7': 'V5', 'SW8': 'U4', 'SW9': 'V2', 'SW10': 'U2', 'SW11': 'T3', 'SW12': 'T1', 'SW13': 'R3', 'SW14': 'P3', 'SW15': 'P4'}, 'LED': {'LED0': 'T8', 'LED1': 'V9', 'LED2': 'R8', 'LED3': 'T6', 'LED4': 'T5', 'LED5': 'T4', 'LED6': 'U7', 'LED7': 'U6', 'LED8': 'V4', 'LED9': 'U3', 'LED10': 'V1', 'LED11': 'R1', 'LED12': 'P5', 'LED13': 'U1', 'LED14': 'R2', 'LED15': 'P2'}, 'RGB': {'LED16_R': 'K5', 'LED16_G': 'F13', 'LED16_B': 'F6', 'LED17_R': 'K6', 'LED17_G': 'H6', 'LED17_B': 'L16'}, '7SEG': {'7SEG_CA': 'L3', '7SEG_CB': 'N1', '7SEG_CC': 'L5', '7SEG_CD': 'L4', '7SEG_CE': 'K3', '7SEG_CF': 'M2', '7SEG_CG': 'L6', '7SEG_DP': 'M4', '7SEG_AN0': 'N6', '7SEG_AN1': 'M6', '7SEG_AN2': 'M3', '7SEG_AN3': 'N5', '7SEG_AN4': 'N2', '7SEG_AN5': 'N4', '7SEG_AN6': 'L1', '7SEG_AN7': 'M1'}, 'Button': {'BTN3': 'E16', 'BTN2': 'F15', 'BTN1': 'T16', 'BTN0': 'R10', 'BTND': 'V10'}, 'VGA': {'VGA_RED0': 'A3', 'VGA_RED1': 'B4', 'VGA_RED2': 'C5', 'VGA_RED3': 'A4', 'VGA_GREEN0': 'C6', 'VGA_GREEN1': 'A5', 'VGA_GREEN2': 'B6', 'VGA_GREEN3': 'A6', 'VGA_BLUE0': 'B7', 'VGA_BLUE1': 'C7', 'VGA_BLUE2': 'D7', 'VGA_BLUE3': 'D8', 'VGA_HSYNC': 'B11', 'VGA_VSYNC': 'B12'}, 'UART': {'UART_TXD_IN': 'C4', 'UART_RXD_OUT': 'D4', 'UART_CTS': 'D3', 'UART_RTS': 'E5'}, 'PS2': {'PS2_CLK': 'F4', 'PS2_DATA': 'B2'}, 'ACL': {'ACL_MISO': 'D13', 'ACL_MOSI': 'B14', 'ACL_SCLK': 'D15', 'ACL_CSN': 'C15', 'ACL_INT1': 'C16', 'ACL_INT2': 'E15'}, 'Temp': {'TMP_SCL': 'F16', 'TMP_SDA': 'G16', 'TMP_INT': 'D14', 'TMP_CT': 'C14'}, 'SD': {'SD_RESET': 'E2', 'SD_CD': 'A1', 'SD_SCK': 'B1', 'SD_CMD': 'C1', 'SD_DAT0': 'C2', 'SD_DAT1': 'E1', 'SD_DAT2': 'F1', 'SD_DAT3': 'D2'}, 'Audio': {'AUD_PWM': 'A11', 'AUD_SD': 'D12', 'MIC_CLK': 'J5', 'MIC_DATA': 'H5', 'MIC_LRSEL': 'F5'}, 'QSPI': {'QSPI_SCK': 'E9', 'QSPI_D0': 'K17', 'QSPI_D1': 'K18', 'QSPI_D2': 'L14', 'QSPI_D3': 'M14', 'QSPI_CSN': 'L13'}, 'CLK, Reset': {'CPU_RESETN': 'C12', 'Clock': 'E3'}}, {'Name': 'Nexys 4 DDR', 'Switch': {'SW0': 'J15', 'SW1': 'L16', 'SW2': 'M13', 'SW3': 'R15', 'SW4': 'R17', 'SW5': 'T18', 'SW6': 'U18', 'SW7': 'R13', 'SW8': 'T8', 'SW9': 'U8', 'SW10': 'R16', 'SW11': 'T13', 'SW12': 'H6', 'SW13': 'U12', 'SW14': 'U11', 'SW15': 'V10'}, 'LED': {'LED0': 'H17', 'LED1': 'K15', 'LED2': 'J13', 'LED3': 'N14', 'LED4': 'R18', 'LED5': 'V17', 'LED6': 'U17', 'LED7': 'U16', 'LED8': 'V16', 'LED9': 'T15', 'LED10': 'U14', 'LED11': 'T16', 'LED12': 'V15', 'LED13': 'V14', 'LED14': 'V12', 'LED15': 'V11'}, 'RGB': {'LED16_B': 'R12', 'LED16_G': 'M16', 'LED16_R': 'N15', 'LED17_B': 'G14', 'LED17_G': 'R11', 'LED17_R': 'N16'}, '7SEG': {'7SEG_CA': 'T10', '7SEG_CB': 'R10', '7SEG_CC': 'K16', '7SEG_CD': 'K13', '7SEG_CE': 'P15', '7SEG_CF': 'T11', '7SEG_CG': 'L18', '7SEG_DP': 'H15', '7SEG_AN0': 'J17', '7SEG_AN1': 'J18', '7SEG_AN2': 'T9', '7SEG_AN3': 'J14', '7SEG_AN4': 'P14', '7SEG_AN5': 'T14', '7SEG_AN6': 'K2', '7SEG_AN7': 'U13'}, 'Button': {'BTN3': 'N17', 'BTN2': 'M18', 'BTN1': 'P17', 'BTN0': 'M17', 'BTND': 'P18'}, 'VGA': {'VGA_RED0': 'A3', 'VGA_RED1': 'B4', 'VGA_RED2': 'C5', 'VGA_RED3': 'A4', 'VGA_GREEN0': 'C6', 'VGA_GREEN1': 'A5', 'VGA_GREEN2': 'B6', 'VGA_GREEN3': 'A6', 'VGA_BLUE0': 'B7', 'VGA_BLUE1': 'C7', 'VGA_BLUE2': 'D7', 'VGA_BLUE3': 'D8', 'VGA_HSYNC': 'B11', 'VGA_VSYNC': 'B12'}, 'UART': {'UART_TXD_IN': 'C4', 'UART_RXD_OUT': 'D4', 'UART_CTS': 'D3', 'UART_RTS': 'E5'}, 'PS2': {'PS2_CLK': 'F4', 'PS2_DATA': 'B2'}, 'ACL': {'ACL_MISO': 'E15', 'ACL_MOSI': 'F14', 'ACL_SCLK': 'F15', 'ACL_CSN': 'D15', 'ACL_INT1': 'B13', 'ACL_INT2': 'C16'}, 'Temp': {'TMP_SCL': 'C14', 'TMP_SDA': 'C15', 'TMP_INT': 'D13', 'TMP_CT': 'B14'}, 'SD': {'SD_RESET': 'E2', 'SD_CD': 'A1', 'SD_SCK': 'B1', 'SD_CMD': 'C1', 'SD_DAT0': 'C2', 'SD_DAT1': 'E1', 'SD_DAT2': 'F1', 'SD_DAT3': 'D2'}, 'Audio': {'AUD_PWM': 'A11', 'AUD_SD': 'D12', 'MIC_CLK': 'J5', 'MIC_DATA': 'H5', 'MIC_LRSEL': 'F5'}, 'QSPI': {'QSPI_D0': 'K17', 'QSPI_D1': 'K18', 'QSPI_D2': 'L14', 'QSPI_D3': 'M14', 'QSPI_CSN': 'L13'}, 'CLK, Reset': {'CPU_RESETN': 'C12', 'Clock': 'E3'}}]¶

browse()¶

Browse event. Parses the chosen VHDL file.

Returns

chosen_portlist = {}¶

flattened_portlist = {}¶

generate_constraint()¶

Generate constraint event.

Returns

generate_tb()¶

Generate testbench event.

Returns

input_file_name = ''¶

input_file_path = ''¶

onboard_clock_clicked()¶

Clock selection event.

Returns

output_file_path = ''¶

picked_board(index)¶

Event on choosing development board. Hides clock selection if custom board has been chosen.

Parameters: index (class) – Object of chosen element in combobox.
Returns

pinout_name_list = []¶

print_help()¶

Prints help in gui.

Returns

project_path = ''¶

retranslateUi(MainWindow)¶

Additional setting for main window. Mostly text and callback function setting to trigger events.

Parameters: MainWindow (class) – Object of main window instance
Returns

set_items_in_table(current_row_id)¶

Sets every element in I/O table to tree combobox and adds groups to it.

Parameters: current_row_id (int) – index of the current element in I/O table.
Returns

setup_ui(MainWindow)¶

Sets the gui. Creates the window, creates menu, creates table and comboboxes and corresponding labels

Parameters: MainWindow (class) – Object of main window instance
Returns

using_onboard_clock = False¶

xdc_ports = {}¶

fpgatools.FPGA_Tools.showdialog(message, severity='warning')¶

Messagebox dialog. Prints message to the user.

Parameters

message (str) – Message of the messagebox.
severity (str) – Severity of the message: warning/info/critical.

Returns

fpgatools.FPGA_Tools.showwindow()¶

Main funciton. Creates GUI. Starts application.

Returns

fpgatools.gen_and_parse module¶

fpgatools.gen_and_parse.create_tb(libs, ports, module_name, output_path)¶

Generates testbench content and writes to given output path.

Parameters

libs (list) – list of included libraries
ports (dict) – dictionary of ports {‘<port name>’: ‘<port content>’}
module_name (str) – name of the source module.
output_path (str) – path of the output file

Returns

fpgatools.gen_and_parse.delete_comments(file_content)¶

Removes all comments from the given string.

Parameters: file_content (str) – file content
Return str: same content without comments

fpgatools.gen_and_parse.generate_tb(filepath, output_path)¶

Generates testbench. This function needed due to logical belonging.

Parameters

filepath (str) – input file path
output_path (str) – output file path

Returns

fpgatools.gen_and_parse.get_stuff(filepath)¶

High level parse function. Calls every parser and gives back queried values.

Parameters: filepath (str) – Source VHDL module path
Return tuple: (<{<port name>: [<port content>]}>, ‘<module name>’, [<libraries>])

fpgatools.gen_and_parse.parse_entity(file_content)¶

Parses entity of the given VHDL file.

Parameters: file_content (str) – file content
Return tuple: (<list of ports>, <name of the module>)

fpgatools.gen_and_parse.parse_libs(file_content)¶

Query libraries from given string.

Parameters: file_content (str) – file content
Return list: list of the found libraries

fpgatools.gen_and_parse.read_file_content(path)¶

Reads content of given path.

Parameters: path (str) – file path
Return str: Content of the given file as string.

fpgatools.gen_and_parse.write_const_to_file(port_and_package_dict, output_path, use_onboard_clock, clock_var)¶

Generates constraint file and writes it to file.

Parameters

port_and_package_dict (dict) – peer to peer binding of signals and I/O
output_path (str) – output file path
use_onboard_clock (bool) – clock selection boolean
clock_var (str) – name of the selected clock port

Returns